1. Field of the Invention
The present invention relates to superscalar reduced instruction set computers (RISC), more particularly, the present invention relates to a register renaming circuit for superscalar RISC computers.
2. Background Art
A more detailed description of some of the basic concepts discussed in this application is found in a number of references, including Mike Johnson, Superscalar Microprocessor Design (Prentice-Hall, Inc., Englewood Cliffs, N.J., 1991) (hereafter Johnson); John L. Hennessy et al., Computer Architecture—A Quantitative Approach (Morgan Kaufmann Publishers, Inc., San Mateo, Calif. 1990). Johnson's text, particularly Chapters 2, 6 and 7 provide an excellent discussion of the register renaming issues addressed by the present invention.
A major consideration in a superscalar RISC processor is how to execute multiple instructions in parallel and out-of-order, without incurring data errors due to dependencies inherent in such execution. Data dependency checking, register renaming and instruction scheduling are integral aspects of the solution. A detailed discussion of storage conflicts, register renaming and dependency mechanisms is found in related U.S. Pat. No. 5,497,499 to Garg et al. (hereinafter referred to as the '499 patent).
The '499 patent discloses a register renaming circuit (RRC) having a fixed instruction window. In the fixed instruction window, dependency checking and resource assignment is done on the same set of instructions until all the instructions in the set are completed. This means that there is a fixed relationship between each instruction's position in the instruction stream and the instruction number used for resource assignment.
For example, in an instruction stream with an instruction window of 4 instructions every fourth instruction maps to instruction A (i.e., the first instruction in the window). This technique makes re-mapping of instruction very simple. In this case a 4-to-1 multiplexer is all that is necessary for each resource to forward a single instruction to that resource. However, the fixed format requires that the instruction window be advanced by a fixed amount, which results in somewhat inefficient processing.
When an instruction retires (an instruction can retire after it has been executed without exception and when all previous instructions have been executed and their results are stored in the register file), its result is moved into a main register file (i.e., the programmable visible register file) and if any instructions were dependent on that instruction, their renamed sources are not needed anymore. In the architecture disclosed in the '499 patent, all instructions' sources are renamed every cycle. This renaming technique requires many comparators for performing the dependency checks. More specifically, the source register addresses of each instruction must be compared to the destination register addresses of all preceding instructions in the instruction window every cycle.
What is desired is a more efficient register renaming technique requiring less comparators and permitting the processor to execute instructions in parallel and out of order.